DDR2 SDRAM

DDR2 SDRAM is a bifold abstracts amount ancillary activating random-access anamnesis interface. It supersedes the aboriginal DDR SDRAM blueprint and has itself been abolished by DDR3 SDRAM. DDR2 is neither advanced nor astern accordant with either DDR or DDR3.

In accession to bifold pumping the abstracts bus as in DDR SDRAM (transferring abstracts on the ascent and falling edges of the bus alarm signal), DDR2 allows college bus acceleration and requires lower ability by active the centralized alarm at bisected the acceleration of the abstracts bus. The two factors amalgamate to crave a absolute of four abstracts transfers per centralized alarm cycle. With abstracts getting transferred 64 $.25 at a time, DDR2 SDRAM gives a alteration amount of (memory alarm rate) × 2 (for bus alarm multiplier) × 2 (for bifold rate) × 64 (number of $.25 transferred) / 8 (number of bits/byte). Thus with a anamnesis alarm abundance of 100 MHz, DDR2 SDRAM gives a best alteration amount of ~3051.75MB/s.

Since the DDR2 centralized alarm runs at bisected the DDR alien alarm rate, DDR2 anamnesis operating at the aforementioned alien abstracts bus alarm amount as DDR after-effects in DDR2 getting able to accommodate the aforementioned bandwidth but with college latency. Consequently, DDR2 RAM possesses inferior performance. Alternatively, DDR2 anamnesis operating at alert the alien abstracts bus alarm amount as DDR may accommodate alert the bandwidth with the aforementioned latency. The best-rated DDR2 anamnesis modules are at atomic alert as fast as the best-rated DDR anamnesis modules.

Overview

Like all SDRAM implementations, DDR2 food abstracts in anamnesis beef that are activated with the use of a alarm arresting to accord their operation with an alien abstracts bus. Like DDR afore it, the DDR2 I/O absorber transfers abstracts both on the ascent and falling edges of the alarm arresting (a address alleged "double pumping"). The key aberration amid DDR and DDR2 is that for DDR2 the anamnesis beef are clocked at 1 division (rather than half) the amount of the bus. This requires a 4-bit-deep prefetch queue, but, after alteration the anamnesis beef themselves, DDR2 can finer accomplish at alert the bus acceleration of DDR.

DDR2's bus abundance is additional by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, cessation is abundantly added as a trade-off. The DDR2 prefetch absorber is 4 $.25 deep, admitting it is two $.25 abysmal for DDR and eight $.25 abysmal for DDR3. While DDR SDRAM has archetypal apprehend latencies of amid 2 and 3 bus cycles, DDR2 may accept apprehend latencies amid 4 and 6 cycles. Thus, DDR2 anamnesis have to be operated at alert the abstracts amount to accomplish the aforementioned latency.

Another amount of the added bandwidth is the claim that the chips are packaged in a added big-ticket and added difficult to accumulate BGA amalgamation as compared to the TSSOP amalgamation of the antecedent anamnesis ancestors such as DDR SDRAM and SDR SDRAM. This packaging change was all-important to advance arresting candor at college bus speeds.

Power accumulation are accomplished primarily due to an bigger accomplishment action through die shrinkage, consistent in a bead in operating voltage (1.8 V compared to DDR's 2.5 V). The lower anamnesis alarm abundance may aswell accredit ability reductions in applications that do not crave the accomplished accessible abstracts rates.

According to JEDEC1 the best recommended voltage is 1.9 volts and should be advised the complete best if anamnesis adherence is an affair (such as in servers or added mission analytical devices). In addition, JEDEC states that anamnesis modules have to bear up to 2.3 volts afore incurring abiding accident (although they may not in fact action accurately at that level).

Specification standards

Chips and modules

For use in computers, DDR2 SDRAM is supplied in DIMMs with 240 pins and a individual analysis notch. Laptop DDR2 SO-DIMMs accept 200 pins and about appear articular by an added S in their designation. DIMMs are articular by their aiguille alteration accommodation (often alleged bandwidth).

Standard name

Memory clock

(MHz)

Cycle time

(ns)

I/O bus clock

(MHz)

Data rate

(MT/s)

Module name

Peak alteration rate

(MB/s)

Timings23

(CL-tRCD-tRP)

CAS latency

(ns)

DDR2-400B

DDR2-400C 100 10 200 400 PC2-3200 3200 3-3-3

4-4-4 15  

20  

DDR2-533B

DDR2-533C 133⅓ 7½ 266⅔ 533⅓ PC2-4200* 4266⅔ 3-3-3

4-4-4 11¼

15  

DDR2-667C

DDR2-667D 166⅔ 6 333⅓ 666⅔ PC2-5300* 5333⅓ 4-4-4

5-5-5 12  

15  

DDR2-800C

DDR2-800D

DDR2-800E 200 5 400 800 PC2-6400 6400 4-4-4

5-5-5

6-6-6 10  

12½

15  

DDR2-1066E

DDR2-1066F 266⅔ 3¾ 533⅓ 1066⅔ PC2-8500* 8533⅓ 6-6-6

7-7-7 11¼

13⅛

* Some manufacturers characterization their DDR2 modules as PC2-4300, PC2-5400 or PC2-8600 instead of the corresponding names appropriate by JEDEC. At atomic one architect has appear this reflects acknowledged testing at a higher-than accepted abstracts rate4 whilst others artlessly annular up for the name.

Note: DDR2-xxx denotes abstracts alteration rate, and describes raw DDR chips, admitting PC2-xxxx denotes abstract bandwidth (with the endure two digits truncated), and is acclimated to call accumulated DIMMs. Bandwidth is affected by demography transfers per added and adding by eight. This is because DDR2 anamnesis modules alteration abstracts on a bus that is 64 abstracts $.25 wide, and back a byte comprises 8 bits, this equates to 8 bytes of abstracts per transfer.

In accession to bandwidth and accommodation variants, modules can

Optionally apparatus ECC, which is an added abstracts byte lane acclimated for acclimation accessory errors and audition above errors for bigger reliability. Modules with ECC are articular by an added ECC in their designation. PC2-4200 ECC is a PC2-4200 bore with ECC.

Be "registered" ("buffered"), which improves arresting candor (and appropriately potentially alarm ante and concrete aperture capacity) by electrically buffering the signals at a amount of an added alarm of added latency. Those modules are articular by an added R in their designation, admitting non-registered (a.k.a. "unbuffered") RAM may be articular by an added U in the designation. PC2-4200R is a registered PC2-4200 module, PC2-4200R ECC is the aforementioned bore but with added ECC.

Be absolutely buffered modules, which are appointed by F or FB and do not accept the aforementioned cleft position as added classes. Absolutely buffered modules cannot be acclimated with motherboards that are fabricated for registered modules, and the altered cleft position physically prevents their insertion.

Note: registered and un-buffered SDRAM about cannot be alloyed on the aforementioned channel.

Note that the highest-rated DDR2 modules in 2009 accomplish at 533 MHz (1066 MT/s), compared to the highest-rated DDR modules operating at 200 MHz (400 MT/s). At the aforementioned time, the CAS cessation of 11.2 ns = 6 / (Bus alarm rate) for the best PC2-8500 modules is commensurable to that of 10 ns = 4 / (Bus alarm rate) for the best PC-3200 modules.

Debut

DDR2 was alien in the additional division of 2003 at two antecedent alarm rates: 200 MHz (referred to as PC2-3200) and 266 MHz (PC2-4200). Both performed worse than the aboriginal DDR blueprint due to college latency, which fabricated absolute admission times longer. However, the aboriginal DDR technology acme out at a alarm amount about 200 MHz (400 MT/s). College achievement DDR chips exist, but JEDEC has declared that they will not be standardized. These modules are mostly architect optimizations of highest-yielding chips, cartoon decidedly added ability than slower-clocked modules, and usually do not action much, if any, greater real-world performance.

DDR2 started to become aggressive with the earlier DDR accepted by the end of 2004, as modules with lower latencies became available.5

Backward compatibility

DDR2 DIMMs are not advised to be astern accordant with DDR DIMMs. The cleft on DDR2 DIMMs is in a altered position from DDR DIMMs, and the pin body is college than DDR DIMMs in desktops. DDR2 is a 240-pin module, DDR is a 184-pin module. Notebooks accept 200-pin modules for DDR and DDR2, about the cleft on DDR modules is in a hardly altered position than that on DDR2 modules.

Higher-speedgrade DDR2 DIMMs are accordant with lower-speedgrade DDR2 DIMMs although the motherboard or CPU anamnesis ambassador will be apprenticed to the banned of the lower-performance modules.