Like all SDRAM implementations, DDR2 food abstracts in anamnesis beef that are activated with the use of a alarm arresting to accord their operation with an alien abstracts bus. Like DDR afore it, the DDR2 I/O absorber transfers abstracts both on the ascent and falling edges of the alarm arresting (a address alleged "double pumping"). The key aberration amid DDR and DDR2 is that for DDR2 the anamnesis beef are clocked at 1 division (rather than half) the amount of the bus. This requires a 4-bit-deep prefetch queue, but, after alteration the anamnesis beef themselves, DDR2 can finer accomplish at alert the bus acceleration of DDR.
DDR2's bus abundance is additional by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, cessation is abundantly added as a trade-off. The DDR2 prefetch absorber is 4 $.25 deep, admitting it is two $.25 abysmal for DDR and eight $.25 abysmal for DDR3. While DDR SDRAM has archetypal apprehend latencies of amid 2 and 3 bus cycles, DDR2 may accept apprehend latencies amid 4 and 6 cycles. Thus, DDR2 anamnesis have to be operated at alert the abstracts amount to accomplish the aforementioned latency.
Another amount of the added bandwidth is the claim that the chips are packaged in a added big-ticket and added difficult to accumulate BGA amalgamation as compared to the TSSOP amalgamation of the antecedent anamnesis ancestors such as DDR SDRAM and SDR SDRAM. This packaging change was all-important to advance arresting candor at college bus speeds.
Power accumulation are accomplished primarily due to an bigger accomplishment action through die shrinkage, consistent in a bead in operating voltage (1.8 V compared to DDR's 2.5 V). The lower anamnesis alarm abundance may aswell accredit ability reductions in applications that do not crave the accomplished accessible abstracts rates.
According to JEDEC1 the best recommended voltage is 1.9 volts and should be advised the complete best if anamnesis adherence is an affair (such as in servers or added mission analytical devices). In addition, JEDEC states that anamnesis modules have to bear up to 2.3 volts afore incurring abiding accident (although they may not in fact action accurately at that level).
DDR2's bus abundance is additional by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, cessation is abundantly added as a trade-off. The DDR2 prefetch absorber is 4 $.25 deep, admitting it is two $.25 abysmal for DDR and eight $.25 abysmal for DDR3. While DDR SDRAM has archetypal apprehend latencies of amid 2 and 3 bus cycles, DDR2 may accept apprehend latencies amid 4 and 6 cycles. Thus, DDR2 anamnesis have to be operated at alert the abstracts amount to accomplish the aforementioned latency.
Another amount of the added bandwidth is the claim that the chips are packaged in a added big-ticket and added difficult to accumulate BGA amalgamation as compared to the TSSOP amalgamation of the antecedent anamnesis ancestors such as DDR SDRAM and SDR SDRAM. This packaging change was all-important to advance arresting candor at college bus speeds.
Power accumulation are accomplished primarily due to an bigger accomplishment action through die shrinkage, consistent in a bead in operating voltage (1.8 V compared to DDR's 2.5 V). The lower anamnesis alarm abundance may aswell accredit ability reductions in applications that do not crave the accomplished accessible abstracts rates.
According to JEDEC1 the best recommended voltage is 1.9 volts and should be advised the complete best if anamnesis adherence is an affair (such as in servers or added mission analytical devices). In addition, JEDEC states that anamnesis modules have to bear up to 2.3 volts afore incurring abiding accident (although they may not in fact action accurately at that level).
No comments:
Post a Comment